1. Field of the Invention
The present invention generally relates to a method for planarizing bottom-anti-reflective coating (BARC) layer, and more particularly to a method for forming dual damascene structure with improved critical dimension (CD) control for vias by planarizing the BARC layer.
2. Description of the Prior Art
As feature sizes shrink, more devices can be built per unit substrate area. The multi-layer interconnects are employed in order to accommodate higher densities as device dimensions shrink well below one micron design rules. Through advanced semiconductor processing techniques, integrated circuit devices with sub-micron and sub-half-micron features have driven the need for multi-layer interconnects. At the same time, the size of interconnect structures will also need to shrink, in order to accommodate the smaller dimensions. Thus, as integrated circuit technology advances into the deep sub-micron range, more advanced interconnect architecture and application are required.
The damascene integration scheme is one such architecture to satisfy this need. There are two major classes of damascene processes: single-damascene and dual-damascene. A single damascene process involves making contact to a lower conductive layer by patterning dielectric layer and forming a conducting plug in the dielectric layer, then patterning a second dielectric layer and forming the actual interconnect wiring metallization in the dielectric layer. The dual damascene technology is applied, as integrated circuit technology advances to 0.18 micrometer. In a dual damascene process, the interconnect wiring and plug are formed by patterning both the via and the trench patterns into dielectric layer, then filling them simultaneously with conducting material, such as metal. The dual damascene process offers advantages in process simplification and low manufacturing cost by reducing the process steps required to form the vias and trenches for a given metallization level. The openings, for the wiring of a metallization level and the underlying via connecting the wiring to a lower conducting level, are formed at the same time.
Dual damascene integration requires challenging developments of patterning processes. Both lithography and etch become more difficult due to the complex layer stack and intermediate topography. Therefore, many different dual damascene patterning strategies are possible, leading to a similar topography before the conducting material is placed. Many dual damascene process flows depend upon the sequence of basic etch steps, which defines a dual damascene process flow as self-aligned, via-first, or trench-first. Self-aligned dual damascene (SADD) needs a thick intermediate layer to serve as a photo anti-reflection layer, an etch-stop layer, and a hard mask providing CD control for underlying vias. Because self-aligned vias require almost perfect trench-to-via alignment and the challenge of maintaining a very high selectivity between the dielectric and intermediate stop layer when etching the via, its application is limited. In the via-first dual damascene (VFDD), the via lithography is done first on top of the full stack. After via etching and stripping, the trench photo step is done. In some cases, the bottom of via is covered by organic material to protect the via during the trench etch. In the approach of trench-first dual damascene (TFDD), the trench is masked and etched through the dielectric layer with stop at a timed depth. The via pattern is then aligned with trench and etched through the dielectric layer to the lower conductive layer. The second via lithography process is much more challenging, due to the topography variations, since a variety of trench feature widths and pitches are possible, and achieving a uniform trench with a smooth flat etch front is difficult.
It is well known that reflection control is essential in lithography processing. Unwanted reflections from these underlying materials during the photoresist patterning process cause the resulting photoresist pattern to be distorted. The use of an anti-reflective coating (ARC) is pursued in the integration of dual damascene to prevent distortion of the photoresist pattern. However, as creating topography in the first lithography step, local reflectivity changes occur over the substrate. The use of a single layer resist on this topography results in severe CD variations. This is not only the result of these local reflectivity variations, but also of the severe resist thickness variations, due to changes in feature topography density. A possible solution is the use of an organic bottom-anti-reflective coating (BARC), which helps on one hand to make the reflectivity again more uniform, but on the other hand helps to decrease the step height in topography.
However, in the TFDD or VFDD process, without using a gap-filling material after the first patterning step, this results in profile distortion due to the rough topography. It is noted that, in some cases, the gap-filling process in VFDD creates a fence problem, which is a residue when the trench is etched. Another approach with partial gap-filling still cannot prevent the profile distortion, because it is difficult to predict how planarization is required in a process, since partial filled BARC already reduce reflectivity changes and resist thickness swing. Therefore, in most cases, all possible feature densities are completely filled with BARC material. In the conventional technique, this requires planarizing BARC with lower viscosity or multiple coating of planarizing BARC. That is to say, the planarization is very important for the second lithography process in dual damascene patterning, profile distortion occurs if there is no further planarization on coated BARC. As shown in FIG. 1, the profile of a via pattern transferred photoresist 18 formed on a rough BARC surface 16 which fills the trench in the dielectric layer 14 on a substrate 10 having a conductive structure 12 is distortion. The main issue of planarization on the first created topography is that all sizes are possible in combination with all pitches. This means that in principle a minimum size isolated feature can be present as well as a minimum spacing between very large features. Referring to FIG. 2, showing a dielectric layer 24 with trenches is formed on a substrate 20 having conductive structures 22 by using BARC 26 as the gap-filling material, a rough topography is presented. Filling both isolated and dense features in a similar way is very difficult. The BARC coating level is very different depending very much on the feature density and size.
Besides, investigation on planarization of BARC level has disclosed that after coated BARC material cross-linking to achieve the goal of anti-reflecting, it is difficult to further planarize the BARC level to get smoother topography due to its hardness. Thus, during implanting dual damascene process, it is desired to get planar topography prior to executing the second lithography process to improve the profile distortion and the CD control for vias because of poor film topography and different thickness variation in BARC layer.
The present invention is directed to a method for planarizing a BARC layer in the dual damascene process. For forming dual damascene interconnect structure, by use of the present invention, a planar topography of BARC layer is achieved by chemical mechanical polishing. The essential part of the present invention is to apply low temperature baking of the coated BARC layer before BARC material cross-links and induces the anti-reflective characteristics. Then, the BARC layer is planarized by chemical mechanical polishing. A high temperature baking of the BARC layer is provided before coating the photoresist, so the BARC layer is controlled with minimized variation in surface level and has the anti-reflective characteristic. Thus, the profile distortion on via and the CD control for via are improved by patterning via on a planar surface with anti-reflective characteristic.
It is another object of this invention that a method for chemical mechanical polishing BARC layer is provided.
It is a further object of this invention that a method for improving the CD control for vias by performing via lithography on a planar BARC surface in dual damascene process is provided.
It is another further object of this invention that a method for reducing the fence effect by preventing photoresist from reacting with dielectric film of low k material in the opening of forming the dual damascene structure is provided.
In accordance with the present invention, in one embodiment, a method for forming dual damascene interconnect structure with improved CD control for vias by planarizing BARC layer is disclosed. The method comprises a step of providing a substrate having a conductive structure. Then, a dielectric layer is formed on the substrate. A first patterned photoresist defining a first opening is formed on the dielectric layer. Then, by using the first patterned photoresist as a mask a portion of the dielectric layer is etched to a first depth. Next, the first patterned photoresist is removed. Then, a bottom-anti-reflective coating (BARC) layer is formed on the dielectric layer and the first opening is filled with the bottom-anti-reflective coating. Then, the BARC layer is baked at a first temperature, such that the BARC layer is soft enough to be planarized. Next, the BARC layer is chemical mechanical polished to expose the dielectric layer. Then, the BARC layer is baked at a second temperature to have antireflective ability. A second patterned photoresist defines a second opening is formed on the dielectric layer. Then, the BARC layer and the dielectric layer are etched to expose the conductive structure of the substrate by using the second photoresist as a mask. Next, the second patterned photoresist and the BARC layer are removed. Then, the first opening and the second opening are filled with a conductive material to form a conductive layer.